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Cybersecurity IP Core
Hardware-accelerated cryptography — side-channel hardened.
Overview
A drop-in hardware accelerator for symmetric and asymmetric cryptography and secure boot — built for defense electronics and secure-element SoCs.
Hardware acceleration for AES, SHA, ECC and RSA primitives, plus a secure boot block. Designed constant-time and side-channel hardened from the first line of RTL — security is not a wrapper, it's the architecture.
What's included
Features
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AES-128 / 256, SHA-2 / 3
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ECC (P-256, P-384), RSA-2048 / 4096
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True random number generator interface
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AXI / AHB wrappers
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Security white paper
Spec sheet
At a glance
InterfaceAXI4-Lite / AHB-Lite
AlgorithmsAES, SHA-2/3, ECC, RSA
TargetsFPGA + 28/40nm ASIC
ComplianceFIPS-aligned
Full numbers, gate counts, and target-node performance disclosed under NDA.
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